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The most critical section of the FPGA subsystem design was the linear interpolation section.
Although this was mathematically the simplest part of the entire project, implementing it on the
FPGA proved to be somewhat complex. The equation that this section used to calculate the
current values was:
(Previous position) – (Next position) x (Current time step) + (Previous position)
(Previous time) – (Next time)
Equation 1: Basic linear interpolation used in FPGA calculations
The interpolation section was implemented using schematic entry exclusively (no VHDL
written). As in the rest of the design, the interpolation section used fixed-point arithmetic, which
added to the difficulty by complicating changes to the design. Once the interpolation section was
completed, the wrap-around problem was discovered, and the whole interpolation design had to
be reconsidered.
The wrap-around problem arose from the fact that fractional code phases were used instead of
whole and fractional numbers. This was done to avoid having to transmit and operate on the
extremely large number of the repetitions of the C/A code, which would be a waste of space on
the FPGA. Since only fractional numbers were used, the transmitted values would only go from
0 to 1023. This meant that if the signal being generated needed to go into the next whole code
cycle, the value used for interpolation would result in a slope in the wrong direction. See Figure
4 for an illustration of this phenomenon.
To avoid this problem, flags needed to be sent from the PC side when the code phase crossed
over into a new code cycle. This problem was fixed in the interpolator by using a combination
12
of subtractors, adders, and multiplexers in conjunction with the two flags sent from the PC. With
this method, alternate values were always calculated to account for overflow (underflow was
never checked for correctness), and the flags and carry bits from the subtractors were used to
select whether or not the adjusted values should be used instead of the standard interpolated
values. The modified interpolator did work for overflow, and the underflow condition was never
completely implemented and verified due to lack of time. However, a problem occurred in the
project file, and the updated version was corrupted. Time did not allow for this problem to be
fixed appropriately, so the current version of the project still contains the original interpolator
without wrap-around protection.

FPGA calculations

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