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The majority of work on the RF subsystem was left unfinished due to time constraints. Some
experiments were performed in the RF lab to confirm that the signals coming from the D/A
converter could be appropriately upconverted and attenuated to the proper frequencies and signal
power levels. There was not a great deal of design involved with this section, and the only major
issue was getting the right parts, such as a mixer that could operate with the necessary input and
output frequency ranges. Some testing was done on the FPGA output pins to determine the
characteristics of the signals at the input to the D/A converter, and this experiment led to one
minor addition to the project. As a result of the high sampling rate (8.184 MHz), the signals at
the output pins, which are 0V to 3.3V signals, show a large amount of overshoot and ringing.
The voltage levels on the high side did not present any problems, but on the falling edges of the
signal, the level approached -2V. Since the absolute maximum rating for the D/A converter was
-0.3V below ground, the FPGA output was not safe to run into the D/A converter. In order to
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solve this problem, a germanium diode clipping circuit was proposed to prevent the levels from
going too low and damaging the D/A converter. An individual version of this circuit was tested
and validated, but 11 of these circuits would be required for full scale operation, one for each of
ten bits and one for the sample clock.