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The second major area of focus was the FPGA subsystem. This begins with the communication
setup. The communication was never established in lab, but a methodology was established for
parallel communication. The data for each satellite required 4 bytes total. These bytes were
broken up to carry different types of data in order to utilize space effectively. The required data
included the satellite ID number, signal amplitude, fractional code phase, and two flags to
indicate overflow and underflow for the linear interpolation algorithm. The satellite number
required five bits because there are 32 satellites total. The signal amplitude required seven bits.
This was a design choice that was made because it was believed to provide enough dynamic
range to the signal amplitude. The code phase required 18 bits, 10 integer to account for all 1023
chips of the code, and 8 fractional to provide enough resolution between data points. The two
flags each required one bit each as one would expect.
The transmitted data was set to update at 2 KHz. This allowed a reasonable communication data
rate while not requiring excessive interpolation on the FPGA. The communication scheme was
to send the four bytes for each satellite in a predefined order so that no further encoding would
be necessary to separate the data. Each time data was read in for a new satellite (channel), the
data would be stored in a unique register on the FPGA. At the end of the 2 KHz update cycle,
the new values would be shifted into the interpolator, and communication would continue for the
next set of data. All of this was set to be controlled by handshaking between the FPGA and the
PC using a Centronics printer interface, although this was never implemented in practice.